1. Field
This disclosure relates generally to semiconductor memories, and more specifically, to a layout for a dual port static random access memory (SRAM) cell.
2. Related Art
Static random access memories are generally used in applications requiring high speed. A dual port SRAM may include more than one word line and/or more than one pairs of bit lines. FIG. 1 illustrates a schematic diagram of a prior art dual port SRAM cell having access transistors, or pass gates PG1-PG4, pull-up transistors PU1 and PU2, and pull-down transistors PD1-PD4. The SRAM cell of FIG. 1 is based on a conventional six transistor single port SRAM cell except that the SRAM cell of FIG. 1 has two parallel-connected pull-down transistors coupled to each storage node N1 and N2 instead of one very wide transistor, and two word lines. The pull-up and pull-down transistors are coupled to form two cross-coupled inverters with the connections of input and output terminals of the inverters forming storage nodes. The storage nodes are coupled to bit line pairs BL1/BLB1 or BL2/BLB2 via one of the word lines WL1 or WL2. A data bit may be stored on storage nodes N1 and N2 as complementary logic states.
FIG. 2 illustrates a prior art layout of a dual port SRAM cell. The dual port SRAM layout of FIG. 2 is generally based on a standard single port six transistor SRAM cell with reference numerals corresponding to elements in FIG. 1. In FIG. 2, active regions formed in a substrate are indicated using cross-hatching and polysilicon features formed above the active regions are indicated using double cross-hatching. Bit lines, word lines, and power supply conductors are formed in a metal layer above the polysilicon features. In the layout of FIG. 2, access transistors PG1 and PG4 are added at each extremity of the layout design of FIG. 2. The two additional access transistors allow two independent word lines WL1 and WL2 to access the memory cell storage nodes N1 and N2. However, simply adding two additional access transistors to create a dual port cell from a single port design may create issues that become more severe with smaller feature sizes and lower power supply voltages. For example, the additional access transistors PG1 and PG4 may have a significant systematic mismatch due to asymmetry with access transistors PG2 and PG3 causing the access transistors PG1 and PG 4 to produce significantly less drain current. Pass gate PG4 has a longer path to storage node N2 than pass gate PG 3. Also, lithography variations cause an effective gate width difference between the pull-down transistors PD1 and PD2 and access transistors PG2 and PG3 to adversely affect read and write margins. In addition, as can be seen in FIG. 2 the layout for the prior art SRAM cell is very wide with respect to its height, causing increased parasitic interconnection capacitance.
Therefore, what is needed is an SRAM cell layout that solves the above problems.